SAN JOSE, CALIFORNIA –
Media OutReach Newswire – 22 November 2024 –
MIPS, a leading developer of efficient and configurable IP compute cores, announced today the general availability (GA) launch of the MIPS P8700 Series RISC-V Processor. Designed to meet the low-latency, highly intensive data movement demands of the most advanced automotive applications such as ADAS and Autonomous Vehicles (AVs), the P8700 delivers industry-leading accelerated compute, power efficiency and scalability.
Typical solutions for ADAS and autonomous driving rely on a brute-force approach of embedding a higher number of cores at higher clock rates driving synthetic, albeit unrealistic and unrealized performance. The P8700 with its multi-threaded and power-efficient architecture allows MIPS customers to implement fewer CPU cores and much lower thermal design power (TDP) than the current market solutions, thereby allowing OEMs to develop ADAS solutions in an affordable and highly scalable manner. It also mitigates the system bottlenecks of data movement inefficiency by providing highly efficient, optimized and lower power latency sensitive solution specifically tailored for interrupt laden multi-sensor platforms.
For L2+ ADAS systems with AI Autonomous software stack, the MIPS P8700 can also offload core processing elements that cannot be easily quantized in deep learning and reduced by sparsity-based convolution processing functions, resulting in >30% better AI Stack software utilization and efficiency.
“The automotive market demands CPUs which can process a large amount of data from multiple sensors in real-time and feed the AI Accelerators to process in an efficient manner said Sameer Wasson, CEO of MIPS. “The MIPS Multi-threading and other architectural hooks tailored for automotive applications, make it a compelling core for data intensive processing tasks. This will enable Automotive OEMs to have high performance compute systems which consume less power and better utilize AI Accelerators.”
The MIPS P8700 core, featuring multi-core/multi-cluster and multi-threaded CPU IP based on the RISC-V ISA, is now progressing toward series production with multiple major OEMs. Key customers like Mobileye (Nasdaq: MBLY) have embraced this approach for future products for self-driving vehicles and highly automated driving systems.
“MIPS has been a key collaborator in our success with the EyeQ™ systems-on-chip for ADAS and autonomous vehicles,” said Elchanan Rushinek, executive vice president of engineering for Mobileye. “The launch of the MIPS P8700 RISC-V core will help drive our continued development for global automakers, enabling greater performance and excellent efficiency in cost and power usage.”
The P8700 Series is a high-performance out-of-order processor that implements the RISC-V RV64GC architecture, including new CPU and system-level features designed for performance, power, area form factors and additional proven features built on legacy MIPS micro-architecture deployed in more than 30+ car models today across the global OEM market. Engineered to deliver industry-leading compute density, MIPS’ latest processor harnesses three key architectural features, including:
- MIPS Out-of-Order Multi-threading – enables execution of multiple instructions from multiple threads (harts) every clock cycle, providing higher utilization and CPU efficiency.
- Coherent Multi-Core, Multi-Cluster – The P8700 Series scales up to 6 coherent P8700 cores in a cluster with each cluster supporting direct attach accelerators.
- Functional Safety – designed to meet the ASIL-B(D) functional safety standard (ISO26262) by incorporating several fault detection capabilities such as end-to-end parity protection on address and data buses, parity protection on software visible registers, fault bus for reporting faults to the system, and more
The MIPS P8700 processor is now available to the broader market, with key partnerships already in place. Shipments with OEM launches are expected shortly.
For more information about the MIPS P8700, please visit
https://mips.com/markets/automotive/.
Hashtag: #MIPS
The issuer is solely responsible for the content of this announcement.
